SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 111

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.4.2
4.4.3
ARM DDI 0029G
CPA
0
0
1
1
The ARM7TDMI processor
Coprocessor signaling
CPB
0
1
0
1
Response
Coprocessor present
Coprocessor busy
Invalid response
Coprocessor absent
Coprocessor instructions progress down the ARM7TDMI core pipeline in step with the
coprocessor pipeline. A coprocessor instruction is executed if the following are true:
1.
2.
3.
If all these requirements are met, the ARM7TDMI core signals by taking nCPI LOW,
this commits the coprocessor to the execution of the coprocessor instruction.
The coprocessor responses are listed in Table 4-3.
The coprocessor instruction has reached the Execute stage of the pipeline. It
might not if it is preceded by a branch.
The ARM7TDMI processor cannot execute the instruction because the
instruction is in the coprocessor or undefined part of the instruction set.
The instruction has passed its conditional execution tests.
Copyright © 1994-2001. All rights reserved.
Remarks
If a coprocessor can accept an instruction, and can start that instruction
immediately, it must signal this by driving both CPA and CPB LOW. The
ARM7TDMI processor then ignores the coprocessor instruction and
executes the next instruction as normal.
If a coprocessor can accept an instruction, but is currently unable to process
that request, it can stall the ARM7TDMI processor by asserting busy-wait.
This is signaled by driving CPA LOW, but leaving CPB HIGH. When the
coprocessor is ready to start executing the instruction it signals this by
driving CPB LOW. This is shown in Figure 4-1 on page 4-8.
-
If a coprocessor cannot accept the instruction currently in Decode it must
leave CPA and CPB both HIGH. The ARM7TDMI processor takes the
undefined instruction trap.
Table 4-3 Summary of coprocessor signaling
Coprocessor Interface
4-7