SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 244

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B.8.2
B.8.3
B-26
Determining system state
Exit from debug state
To meet the dynamic timing requirements of the memory system, any attempt to access
system state must occur synchronously to it. The ARM7TDMI core must be forced to
synchronize back to system speed. This is controlled by the 33rd bit of scan chain 1.
Any instruction can be placed in scan chain 1 with bit 33, the BREAKPT bit, clear. This
instruction is then executed at debug speed. To execute an instruction at system speed,
the instruction prior to it must be scanned into scan chain 1 with bit 33 set.
After the system speed instruction has been scanned into the data bus and clocked into
the pipeline, the RESTART instruction must be loaded into the TAP controller. This
causes the ARM7TDMI core to automatically synchronize back to MCLK, the system
clock, execute the instruction at system speed, and then re-enter debug state and switch
itself back to the internally generated DCLK. When the instruction has completed,
DBGACK is HIGH and the core is switched back to DCLK. At this point, INTEST can
be selected in the TAP controller and debugging can resume.
To determine that a system speed instruction has completed, the debugger must look at
both DBGACK and nMREQ. To access memory, the ARM7TDMI core drives
nMREQ LOW, after it has synchronized back to system speed. This transition is used
by the memory controller to arbitrate if the ARM7TDMI core can have the bus in the
next cycle. If the bus is not available, the core can have its clock stalled indefinitely.
Therefore, the only way to tell that the memory access has completed, is to examine the
state of both nMREQ and DBGACK. When both are HIGH, the access has completed.
Usually, the debugger uses the EmbeddedICE macrocell to control debugging and by
reading the EmbeddedICE macrocell status register, the state of nMREQ and
DBGACK can be determined.
By using system speed load multiples and debug speed store multiples, the system
memory state can be fed back to the debug host.
There are restrictions on which instructions can have the 33rd bit set. The only valid
instructions on which to set this bit are loads, stores, load multiple, and store multiple.
See also Exit from debug state on page B-26. When the core returns to debug state after
a system speed access, bit 33 of scan chain 1 is set HIGH. This gives the debugger
information about why the core entered debug state the first time this scan chain is read.
Leaving debug state involves restoring the internal state of the ARM7TDMI core,
causing a branch to the next instruction to be executed and synchronizing back to
MCLK. After restoring internal state, a branch instruction must be loaded into the
pipeline. See Behavior of the program counter during debug on page B-29 for a
description of how to calculate the branch.
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ARM DDI 0029G