SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 202

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

AC and DC Parameters
7-30
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
cpih
cpms
cps
ctdel
cth
cts
dbe
dbgd
dbgh
dbgrq
dbnen
dbz
dckf
dckfh
dckr
dckrh
dih
dihu
dis
disu
doh
dohu
nCPI hold time from MCLKf
CPA, CPB to nMREQ, SEQ
CPA, CPB setup to MCLKr
TCK to ECLK delay
Config hold time
Config setup time
Data bus enable time from DBEr
MCLKr to DBGACK valid
DGBACK hold time from MCLKr
DBGRQ to DBGRQI valid
DBE to nENOUT valid
Data bus disable time from DBEf
DCLK induced, TCKf to various outputs valid
DCLK induced, various outputs hold from TCKf
DCLK induced, TCKr to various outputs valid
DCLK induced, various outputs hold from TCKr
DIN[31:0] hold time from MCLKf
DIN[31:0] hold time from MCLKf
DIN[31:0] setup time to MCLKf
DIN[31:0] set up time to MCLKf
DOUT[31:0] hold from MCLKf
DOUT[31:0] hold time from MCLKf
Parameter
Copyright © 1994-2001. All rights reserved.
Table 7-23 AC timing parameters used in this chapter (continued)
Parameter
Type
Minimum
Maximum
Minimum
Maximum
Minimum
Minimum
Maximum
Maximum
Minimum
Maximum
Maximum
Maximum
Maximum
Minimum
Maximum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
ARM DDI 0029G
Figure
cross
reference
Figure 7-10
Figure 7-10
Figure 7-10
Figure 7-16
Figure 7-9
Figure 7-9
Figure 7-5
Figure 7-13
Figure 7-13
Figure 7-13
Figure 7-5
Figure 7-5
-
-
-
-
Figure 7-4
Figure 7-8
Figure 7-4
Figure 7-8
Figure 7-3
Figure 7-5
Figure 7-7