SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 109

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.3
ARM DDI 0029G
Pipeline following signals
Every coprocessor in the system must contain a pipeline follower to track the
instructions in the ARM7TDMI processor pipeline. The coprocessors connect to the
configured ARM7TDMI core input data bus, D[31:0] or DIN[31:0], over which
instructions are fetched, and to MCLK and nWAIT.
It is essential that the two pipelines remain in step at all times. When designing a
pipeline follower for a coprocessor, the following rules must be observed:
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•
•
•
Any instructions that are flushed from the ARM7TDMI processor pipeline:
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•
There are no coprocessor instructions in the Thumb instruction set, and so coprocessors
must monitor the state of the TBIT signal to ensure that they do not decode pairs of
Thumb instructions as ARM instructions.
At reset, with nRESET LOW, the pipeline must either be marked as invalid, or
filled with instructions that do not decode to valid instructions for that
coprocessor.
The coprocessor state must only change when nWAIT is HIGH, except during
reset.
An instruction must be loaded into the pipeline on the falling edge of MCLK, and
only when nOPC, nMREQ, and TBIT were all LOW in the previous bus cycle.
These conditions indicate that this cycle is an ARM instruction fetch, so the new
opcode must be read into the pipeline.
The pipeline must be advanced on the falling edge of MCLK when nOPC,
nMREQ and TBIT are all LOW in the current bus cycle.
These conditions indicate that the current instruction is about to complete
execution, because the first action of any instruction performing an instruction
fetch is to refill the pipeline.
never signal on nCPI that they have entered execute
are automatically replaced in the coprocessor pipeline follower by the prefetches
required to refill the core pipeline.
Copyright © 1994-2001. All rights reserved.
Coprocessor Interface
4-5