SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 163

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.14
ARM DDI 0029G
CP
register
status
Single
register
ready
Single
register
not ready
n registers
(n>1)
ready
Coprocessor data transfer from memory to coprocessor
Cycles
1
2
1
2
•
b
b+1
1
2
•
n
n+1
Address
pc+8
alu
pc+12
pc+8
pc+8
pc+8
pc+8
alu
pc+12
pc+8
alu
alu+•
alu+•
alu+•
pc+12
For coprocessor transfer instructions from memory the coprocessor must commit to the
transfer only when it is ready to accept the data. When CPB goes LOW, the processor
produces the addresses and expects the coprocessor to take the data at sequential cycle
rates. The coprocessor is responsible for determining the number of words to be
transferred, and indicates the last transfer cycle by driving CPA and CPB HIGH.
The ARM7TDMI processor spends the first cycle (and any busy-wait cycles) generating
the transfer address, and updates the base address during the transfer cycles.
The cycle timings are listed in Table 6-17 where:
•
•
b represents the busy cycles
n represents the number of registers.
MAS
[1:0]
2
2
2
2
2
2
2
2
2
2
2
2
Copyright © 1994-2001. All rights reserved.
Table 6-17 Coprocessor data transfer instruction cycle operations
nRW
0
0
0
0
0
0
0
0
0
0
0
0
Data
(pc+8)
(alu)
(pc+8)
-
-
-
(alu)
(pc+8)
(alu)
(alu+•)
(alu+•)
(alu+•)
nMREQ
0
0
1
1
1
0
0
0
0
0
0
0
SEQ
0
0
0
0
0
0
0
0
1
1
1
0
nOPC
0
1
0
1
1
1
1
0
1
1
1
1
Instruction Cycle Timings
nCPI
0
1
0
0
0
0
1
0
1
1
1
1
CPA
0
1
0
0
0
0
1
0
0
0
0
1
CPB
0
1
1
1
1
0
1
0
0
0
0
1
6-21