SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 147

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.3
ARM DDI 0029G
Thumb branch with link
A Thumb Branch with Link operation consists of two consecutive Thumb instructions.
Refer to the ARM Architecture Reference Manual for more information.
The first instruction acts like a simple data operation to add the PC to the upper part of
the offset, storing the result in Register 14, LR.
The second instruction which takes a single cycle acts in a similar fashion to the ARM
state branch with link instruction. The first cycle therefore calculates the final branch
destination whilst performing a prefetch from the current PC.
The second cycle of the second instruction performs a fetch from the branch destination
and the return address is stored in R14.
The third cycle of the second instruction performs a fetch from the destination +2,
refilling the instruction pipeline and R14 is modified, with 2 subtracted from it, to
simplify the return to
subroutine work correctly.
The cycle timings of the complete operation are listed in Table 6-2 where:
•
pc is the address of the first instruction of the operation.
Cycle
1
2
3
4
Copyright © 1994-2001. All rights reserved.
Address
pc+4
pc+6
alu
alu+2
alu+4
MAS[1:0]
1
1
1
1
. This makes the
nRW
0
0
0
0
Table 6-2 Thumb long branch with link
Data
(pc+4)
(pc+6)
(alu)
(alu+2)
nMREQ
0
0
0
0
Instruction Cycle Timings
SEQ
1
0
1
1
nOPC
0
0
0
0
type of
6-5