SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 138

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface
5.8
5.8.1
5-16
Debug Communications Channel
DCC registers
The ARM7TDMI processor EmbeddedICE Logic contains a DCC to pass information
between the target and the host debugger. This is implemented as coprocessor 14
(CP14).
The DCC comprises:
•
•
•
These registers are located in fixed locations in the EmbeddedICE Logic register map,
as shown in Figure B-7 on page B-41, and are accessed from the processor using MCR
and MRC instructions to coprocessor 14.
The following sections describe:
•
•
The DCC control register is read-only. It controls synchronized handshaking between
the processor and the debugger. The control register format is shown in Figure 5-6.
a 32-bit communications data read register
a 32-bit wide communications data write register
a 6-bit communications control register for synchronized handshaking between
the processor and the asynchronous debugger.
DCC registers on page 5-16
Communications through the DCC on page 5-17.
Copyright © 1994-2001. All rights reserved.
EmbeddedICE
31 30 29 28 27
0
version
0
0
1
•
Reserved
Figure 5-6 DCC control register format
2
• W R
Control
1
bits
0
DCC data read register
DCC data write register
ARM DDI 0029G