SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 209

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

A.1.3
ARM DDI 0029G
Name
A[31:0]
Addresses
ABE
Address bus enable
ABORT
Memory abort
ALE
Address latch enable
APE
Address pipeline enable
BIGEND
Big endian configuration
Signals
Table A-3 lists and describes all of the signals used for the ARM7TDMI processor.
Copyright © 1994-2001. All rights reserved.
Type
O8
IC
IC
IC
IC
IC
Description
This is the 32-bit address bus. ALE, ABE, and APE are used to control
when the address bus is valid.
The address bus drivers are disabled when this is LOW, putting the
address bus into a high impedance state. This also controls the LOCK,
MAS[1:0], nRW, nOPC, and nTRANS signals in the same way. ABE
must be tied HIGH if there is no system requirement to disable the
address drivers.
The memory system uses this signal to tell the processor that a requested
access is not allowed.
This signal is provided for backwards compatibility with older ARM
processors. For new designs, if address retiming is required, ARM
Limited recommends the use of APE, and for ALE to be connected
HIGH.
The address bus, LOCK, MAS[1:0], nRW, nOPC, and nTRANS
signals are latched when this is held LOW. This allows these address
signals to be held valid for the complete duration of a memory access
cycle. For example, when interfacing to ROM, the address must be valid
until after the data has been read.
Selects whether the address bus, LOCK, MAS[1:0], nRW, nTRANS,
and nOPC signals operate in pipelined (APE is HIGH) or depipelined
mode (APE is LOW).
Pipelined mode is particularly useful for DRAM systems, where it is
desirable to provide the address to the memory as early as possible, to
allow longer periods for address decoding and the generation of DRAM
control signals. In this mode, the address bus does not remain valid to the
end of the memory cycle.
Depipelined mode can be useful for SRAM and ROM access. Here the
address bus, LOCK, MAS[1:0], nRW, nTRANS, and nOPC signals
must be kept stable throughout the complete memory cycle. However,
this does not provide optimum performance.
See Address timing on page 3-14 for details of this timing.
Selects how the processor treats bytes in memory:
•
•
HIGH for big-endian format
LOW for little-endian format.
Table A-3 Signal Descriptions
Signal Description
A-3