SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 240

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B.7
B.7.1
B-22
The ARM7TDMI core clocks
Clock switch during debug
The ARM7TDMI core has two clocks:
•
•
During normal operation, the core is clocked by MCLK and internal logic holds DCLK
LOW. When the ARM7TDMI core is in the debug state, the core is clocked by DCLK
under control of the TAP state machine and MCLK can free-run. The selected clock is
output on the signal ECLK for use by the external system.
When the CPU core is being debugged and is running from DCLK, nWAIT has no
effect.
When the ARM7TDMI core enters debug state, it must switch from MCLK to DCLK.
This is handled automatically by logic in the ARM7TDMI core. On entry to debug state,
the core asserts DBGACK in the HIGH phase of MCLK. The switch between the two
clocks occurs on the next falling edge of MCLK. This is shown in Figure B-5.
The ARM7TDMI core is forced to use DCLK as the primary clock until debugging is
complete. On exit from debug, the core must be enabled to synchronize back to MCLK.
This must be done in the following sequence:
1.
the memory clock, MCLK
an internally TCK generated clock, DCLK.
The final instruction of the debug sequence must be shifted into the data bus scan
chain and clocked in by asserting DCLK.
Note
DBGACK
Copyright © 1994-2001. All rights reserved.
MCLK
DCLK
ECLK
Figure B-5 Clock switching on entry to debug state
Multiplexer
switching point
ARM DDI 0029G