SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 33

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
Halfword data transfer,
Halfword data transfer,
Branch and exchange
Coprocessor register
Data processing and
Single data transfer
Block data transfer
Coprocessor data
Coprocessor data
Software interrupt
Single data swap
immediate offset
register offset
FSR transfer
Multiply long
Undefined
operation
Multiply
transfer
transfer
Branch
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Refer to the ARM Architectural Reference Manual for more information about the ARM
instruction set formats.
0
0 0 0 0 0 0 A S
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
Copyright © 1994-2001. All rights reserved.
1
0
0
0
0
0
1
1
0
1
0
1
1
1
P
P
P
P U S W L
P
0
1
1
L
0
0
1
Opcode
U
U
U
U N W L
CP Opc
1
0
0
CP Opc
U
B
B
0
0
1
W
W
W
A
0
1
S
S
0
0
L
L
L
L
1 1 1 1
RdHi
CRn
CRn
Rn
Rd
Rn
Rn
Rn
Rn
Rn
Rn
1 1 1 1
Ignored by processor
RdLo
CRd
CRd
Rd
Rn
Rd
Rd
Rd
Rd
Rd
Figure 1-5 ARM instruction set formats
Offset
0 0 0 0 1 0 0 1
1 1 1 1 0 0 0 1
0 0 0 0 1 S H 1
Offset
CP#
CP#
CP#
Rs
Rn
Register list
Operand 2
1 0 0 1
1 0 0 1
1 S H 1
CP
CP
Offset
Offset
1
0
1
Introduction
Offset
CRm
CRm
Rm
Rm
Rm
Rm
Rn
1-11