SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 148

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SAM9RL64

Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9RL64

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Instruction Cycle Timings
6.4
6-6
Branch and Exchange
Cycle
1
2
3
A Branch and Exchange (BX) operation takes three cycles and is similar to a branch. In
the first cycle, the branch destination and the new core state are extracted from the
register source, whilst performing a prefetch from the current PC. This prefetch is
performed in all cases, since by the time the decision to take the branch has been
reached, it is already too late to prevent the prefetch.
During the second cycle, a fetch is performed from the branch destination address using
the new instruction width, dependent on the state that has been selected.
The third cycle performs a fetch from the destination address +2 or +4 (dependent on
the new specified state), refilling the instruction pipeline.
The cycle timings are listed in Table 6-3 where:
W and w represent the instruction width before and after the BX respectively. The
width equals four bytes in ARM state and two bytes in Thumb state. For example,
when changing from ARM to Thumb state, W equals four and w equals two
I and i represent the memory access size before and after the BX respectively.
MAS[1:0] equals two in ARM state and one in Thumb state. When changing
from Thumb to ARM state, I equals one and i equals two.
T and t represent the state of the TBIT before and after the BX respectively. TBIT
equals 0 in ARM state and 1 in Thumb state. When changing from ARM to
Thumb state, T equals 0 and t equals 1.
pc + 2W
alu
alu+w
alu + 2w
Address
Copyright © 1994-2001. All rights reserved.
MAS[1:0]
I
i
i
Table 6-3 Branch and exchange instruction cycle operations
nRW
0
0
0
Data
(pc+2W)
(alu)
(alu+w)
nMREQ
0
0
0
SEQ
0
1
1
nOPC
0
0
0
ARM DDI 0029G
T
t
t
TBIT

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