SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 216

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Signal Description
A-10
Name
RANGEOUT0
EmbeddedICE RANGEOUT0
RANGEOUT1
EmbeddedICE RANGEOUT1
RSTCLKBS
Boundary scan Reset Clock
SCREG[3:0]
Scan chain register
SDINBS
Boundary scan serial input data
SDOUTBS
Boundary scan serial output data
SEQ
Sequential address
SHCLKBS
Boundary scan shift clock, phase
one
SHCLK2BS
Boundary scan shift clock, phase
two
Copyright © 1994-2001. All rights reserved.
Type
O4
O4
O4
O4
O4
IC
O4
O4
O4
Description
When the EmbeddedICE watchpoint unit 0 has matched the conditions
currently present on the address, data, and control busses, then this is
HIGH.
This signal is independent of the state of the watchpoint enable control
bit.
RANGEOUT0 changes when ECLK is LOW.
As RANGEOUT0 but corresponds to the EmbeddedICE watchpoint
unit 1.
When either the TAP controller state machine is in the RESET state or
when nTRST is LOW, then this is HIGH. This can be used to reset
external boundary-scan cells.
These reflect the ID number of the scan chain currently selected by the
TAP controller. These change on the falling edge of TCK when the TAP
state machine is in the UPDATE-DR state.
This provides the serial data for an external boundary-scan chain input.
It changes from the rising edge of TCK and is valid at the falling edge of
TCK.
Accepts serial data from an external boundary-scan chain output,
synchronized to the rising edge of TCK.
This must be tied LOW, if an external boundary-scan chain is not
connected.
When the address of the next memory cycle is closely related to that of
the last memory access, this is HIGH.
In ARM state the new address can be for the same word or the next. In
THUMB state, the same halfword or the next.
It can be used, in combination with the low-order address lines, to
indicate that the next cycle can use a fast memory mode (for example
DRAM page mode) or to bypass the address translation system.
Used to clock the master half of the external scan cells and follows
TCK1 when in the SHIFT-DR state of the state machine and scan chain
3 is selected. When not in the SHIFT-DR state or when scan chain 3 is
not selected, this clock is LOW.
As SHCLKBS but follows TCK2 instead of TCK1.
This must be left unconnected, if an external boundary-scan chain is not
connected.
Table A-3 Signal Descriptions (continued)
ARM DDI 0029G