SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 128

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface
5.3
5.3.1
5-6
Debug interface signals
Entry into debug state
There are three primary external signals associated with the debug interface:
•
•
The following sections describe:
•
•
The ARM7TDMI processor is forced into debug state following a breakpoint,
watchpoint, or debug request.
You can use the EmbeddedICE Logic to program the conditions under which a
breakpoint or watchpoint can occur. Alternatively, you can use the BREAKPT signal
to allow external logic to flag breakpoints or watchpoints and monitor the following:
•
•
•
The timing is the same for externally-generated breakpoints and watchpoints. Data must
always be valid on the falling edge of MCLK. When this is an instruction to be
breakpointed, the BREAKPT signal must be HIGH on the next rising edge of MCLK.
Similarly, when the data is for a load or store, asserting BREAKPT on the rising edge
of MCLK marks the data as watchpointed.
When the processor enters debug state, the DBGACK signal is asserted. The timing for
an externally-generated breakpoint is shown in Figure 5-3 on page 5-7.
The following sections describe:
•
•
•
BREAKPT and DBGRQ are system requests for the processor to enter debug
state
DBGACK is used to indicate that the core is in debug state.
DBGEN must be configured HIGH to fully enable the debug features of the
processor. Refer to Disabling EmbeddedICE on page 5-15.
Entry into debug state on page 5-6
Action of the processor in debug state on page 5-9.
address bus
data bus
control signals.
Entry into debug state on breakpoint on page 5-7
Entry into debug state on watchpoint on page 5-8
Entry into debug state on debug request on page 5-8.
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Note
ARM DDI 0029G