SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 169

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Cycle
1
2
3
4
6.18
ARM DDI 0029G
Address
pc+2L
pc+2L
Xn
Xn+4
Xn+8
Undefined instructions and coprocessor absent
MAS
[1:0]
i
i
2
2
When the processor attempts to execute an instruction that neither it nor a coprocessor
can perform (including all undefined instructions) this causes the processor to take the
undefined instruction trap.
Cycle timings are listed in Table 6-21 where:
•
•
•
•
nRW
0
0
0
0
C represents the current mode-dependent value
T represents the current state-dependent value.
Coprocessor instructions are not available in Thumb state.
CPA and CPB are HIGH during the undefined instruction trap.
Note
Copyright © 1994-2001. All rights reserved.
Data
(pc+2L)
-
(Xn)
(Xn+4)
nMREQ
1
0
0
0
Table 6-21 Undefined instruction cycle operations
SEQ
0
0
1
1
nOPC
0
0
0
0
nCPI
0
1
1
1
nTRANS
C
C
1
1
Instruction Cycle Timings
Mode
Old
Old
00100
00100
TBIT
T
T
0
0
6-27