SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 113

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.4.5
ARM DDI 0029G
Coprocessor register transfer instructions
Execute stage
Decode stage
It is essential that any action taken by the coprocessor while it is busy-waiting is
idempotent. This means that the actions taken by the coprocessor must not corrupt the
state of the coprocessor, and must be repeatable with identical results. The coprocessor
can only change its own state once the instruction has been executed.
The ARM7TDMI processor usually returns from processing the interrupt to retry the
coprocessor instruction. Other coprocessor instructions can be executed before the
interrupted instruction is executed again.
The coprocessor register transfer instructions, MCR and MRC, are used to transfer data
between a register in the ARM7TDMI processor register bank and a register in the
coprocessor register bank. An example sequence for a coprocessor register transfer is
shown in Figure 4-2.
Fetch stage
D[31:0]
MCLK
nCPI
CPA
CPB
Caution
Copyright © 1994-2001. All rights reserved.
ADD
ADD
SUB
ADD
SUB
Figure 4-2 Coprocessor register transfer sequence
MCR
ADD
SUB
MCR
MCR
SUB
TST
TST
SUB
MCR
SUB
TST
DATA
Coprocessor Interface
SUB
TST
INSTR
SUB
4-9