SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 234

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B.6.5
B-16
Scan chains 0, 1, 2, and 3
TAPSM[3:0], TCK1, and TCK2.The list of scan chain numbers allocated by ARM are
shown in Table B-2 on page B-16. An external scan chain can take any other
number.The serial data stream to be applied to the external scan chain is made present
on SDINBS, the serial data back from the scan chain must be presented to the TAP
controller on the SDOUTBS input. The scan chain present between SDINBS and
SDOUTBS is connected between TDI and TDO whenever scan chain 3 is selected, or
when any of the unassigned scan chain numbers is selected. If there is more than one
external scan chain, a multiplexor must be built externally to apply the desired scan
chain output to SDOUTBS. The multiplexor can be controlled by decoding
SCREG[3:0].
Table B-2 lists the scan chain number allocation.
These enable serial access to the core logic and to EmbeddedICE Logic for
programming purposes. They are described in detail below.
Scan chain 0 and 1
Purpose
Length
Each scan chain cell is fairly simple and consists of a serial register and a multiplexor
as shown in Figure B-4 on page B-17. The scan cells perform two basic functions:
•
CAPTURE
Copyright © 1994-2001. All rights reserved.
Enables access to the processor core for test and debug.
Scan chain 0: 105 bits. Scan chain 1: 33 bits
Table B-2 Scan chain number allocation
Scan chain
number
0
1
2
3
4
8
a
a. To be implemented by ASIC designer.
Function
Macrocell scan test
Debug
EmbeddedICE Logic
programming
External boundary-scan
Reserved
Reserved
ARM DDI 0029G