SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 186

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SAM9RL64

Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9RL64

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
AC and DC Parameters
7.11
7-14
Coprocessor timing
Figure 7-10 shows the ARM7TDMI processor coprocessor timing. The timing
parameters used in Figure 7-10 are listed in Table 7-10.
In Figure 7-10, usually nMREQ and SEQ become valid T
MCLK. In this cycle the core has been busy-waiting for a coprocessor to complete the
instruction. If CPA and CPB change during phase 1, the timing of nMREQ and SEQ
depends on T
2, and so the timing of nMREQ and SEQ is always T
nMREQ
MCLK
nCPI
SEQ
CPA
CPB
Note
Copyright © 1994-2001. All rights reserved.
cpms
. Most systems can generate CPA and CPB during the previous phase
Symbol
T
T
T
T
T
cph
cpi
cpih
cpms
cps
Phase 1
T
cpi
Parameter
CPA,CPB hold time from MCLKr
MCLKf to nCPI valid
nCPI hold time from MCLKf
CPA, CPB to nMREQ, SEQ
CPA, CPB setup to MCLKr
T
cpms
T
cps
Table 7-10 Coprocessor timing parameters
T
cph
Phase 2
Figure 7-10 Coprocessor timing
msd
.
T
msd
cpih
after the falling edge of
Parameter type
Minimum
Maximum
Minimum
Maximum
Minimum
ARM DDI 0029G

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