SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 110

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
4.4
4.4.1
4-6
Coprocessor interface handshaking
The coprocessor
Coprocessor interface handshaking is described as follows:
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The ARM7TDMI core and any coprocessors in the system perform a handshake using
the signals shown in Table 4-2.
These signals are explained in more detail in Coprocessor signaling on page 4-7.
The coprocessor decodes the instruction currently in the Decode stage of its pipeline,
and checks whether that instruction is a coprocessor instruction. A coprocessor
instruction contains a coprocessor number that matches the coprocessor ID of the
coprocessor.
If the instruction currently in the Decode stage is a relevant coprocessor instruction:
1.
2.
The coprocessor can drive CPA and CPB as soon as it decodes the instruction. It does
not have to wait for nCPI to be LOW but it must not commit to execute the instruction
until nCPI has gone LOW.
The coprocessor on page 4-6
The ARM7TDMI processor on page 4-7
Coprocessor signaling on page 4-7
Consequences of busy-waiting on page 4-8
Coprocessor register transfer instructions on page 4-9
Coprocessor data operations on page 4-10
Coprocessor load and store operations on page 4-10.
The coprocessor attempts to execute the instruction.
The coprocessor handshakes with the ARM7TDMI core using CPA and CPB.
Note
Copyright © 1994-2001. All rights reserved.
Signal
nCPI
CPA
CPB
Direction
ARM7TDMI core to coprocessor
Coprocessor to ARM7TDMI core
Coprocessor to ARM7TDMI core
Table 4-2 Handshaking signals
Meaning
NOT coprocessor instruction
Coprocessor absent
Coprocessor busy
ARM DDI 0029G