SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 211

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
Name
CPB
Coprocessor busy
D[31:0]
Data bus
DBE
Data bus enable
DBGACK
Debug acknowledge
DBGEN
Debug enable
DBGRQ
Debug request
DBGRQI
Internal debug request
DIN[31:0]
Data input bus
Copyright © 1994-2001. All rights reserved.
Type
IC
IC
O8
IC
O4
IC
IC
O4
IC
Description
Placed LOW by the coprocessor when it is ready to start the operation
requested by the processor.
It is sampled by the processor when MCLK goes HIGH in each cycle in
which nCPI is LOW.
Used for data transfers between the processor and external memory.
During read cycles input data must be valid on the falling edge of
MCLK.
During write cycles output data remains valid until after the falling edge
of MCLK.
This bus is always driven except during read cycles, irrespective of the
value of BUSEN. Consequently it must be left unconnected if using the
unidirectional data buses.
See Chapter 3 Memory Interface.
Must be HIGH for data to appear on either the bidirectional or
unidirectional data output bus.
When LOW the bidirectional data bus is placed into a high impedance
state and data output is prevented on the unidirectional data output bus.
It can be used for test purposes or in shared bus systems.
When the processor is in a debug state this is HIGH.
A static configuration signal that disables the debug features of the
processor when held LOW.
This signal must be HIGH to allow the EmbeddedICE Logic to function.
This is a level-sensitive input, that when HIGH causes ARM7TDMI core
to enter debug state after executing the current instruction. This allows
external hardware to force the ARM7TDMI core into debug state, in
addition to the debugging features provided by the EmbeddedICE Logic.
See Appendix B Debug in Depth.
This is the logical OR of DBGRQ and bit 1 of the debug control register.
Unidirectional bus used to transfer instructions and data from the
memory to the processor.
This bus is only used when BUSEN is HIGH. If unused then it must be
tied LOW.
This bus is sampled during read cycles on the falling edge of MCLK.
Table A-3 Signal Descriptions (continued)
Signal Description
A-5