SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 214

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Signal Description
A-8
Name
nENOUT
Not enable output
nENOUTI
Not enable output
nEXEC
Not executed
nFIQ
Not fast interrupt request
nHIGHZ
Not HIGHZ
nIRQ
Not interrupt request
nM[4:0]
Not processor mode
nMREQ
Not memory request
nOPC
Not op-code fetch
Copyright © 1994-2001. All rights reserved.
Type
O4
O4
O4
IC
O4
IC
O4
O4
O8
Description
During a write cycle, this signal is driven LOW before the rising edge of
MCLK, and remains LOW for the entire cycle. This can be used to aid
arbitration in shared bus applications.
See Chapter 3 Memory Interface.
During a coprocessor register transfer C-cycle from the EmbeddedICE
communications channel coprocessor to the ARM core, this signal goes
LOW. This can be used to aid arbitration in shared bus systems.
This is HIGH when the instruction in the execution unit is not being
executed because, for example, it has failed its condition code check.
Taking this LOW causes the processor to be interrupted if the appropriate
enable in the processor is active. The signal is level-sensitive and must be
held LOW until a suitable response is received from the processor. nFIQ
can be synchronous or asynchronous to MCLK, depending on the state
of ISYNC.
When the current instruction is HIGHZ this signal is LOW. This is used
to place the scan cells of that scan chain in the high impedance state.
This must be left unconnected, if an external boundary-scan chain is not
connected.
As nFIQ, but with lower priority. Can be taken LOW to interrupt the
processor when the appropriate enable is active. nIRQ can be
synchronous or asynchronous, depending on the state of ISYNC.
These are the inverse of the internal status bits indicating the current
processor mode.
When the processor requires memory access during the following cycle
this is LOW.
When the processor is fetching an instruction from memory this is LOW.
This is one of the signals controlled by APE, ALE, and ABE.
Table A-3 Signal Descriptions (continued)
ARM DDI 0029G