SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 232

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B.6
B.6.1
B.6.2
B-14
Test data registers
Bypass register
ARM7TDMI core device IDentification (ID) code register
31
There are seven test data registers that can connect between TDI and TDO:
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•
•
•
•
In the following test data register descriptions, data is shifted during every TCK cycle.
Purpose
Length
Operating mode
Purpose
Length
Contact your supplier for the correct device identification code.
Operating mode
Version
Bypass register on page B-14
ARM7TDMI core device IDentification (ID) code register on page B-14
Instruction register on page B-15
Scan path select register on page B-15
Scan chains 0, 1, 2, and 3 on page B-16.
28
Copyright © 1994-2001. All rights reserved.
27
Bypasses the device during scan testing by providing a path
between TDI and TDO.
1 bit.
When the BYPASS instruction is the current instruction in the
instruction register, serial data is transferred from TDI to TDO in
the SHIFT-DR state with a delay of one TCK cycle. There is no
parallel output from the bypass register.
A logic 0 is loaded from the parallel input of the bypass register in
the CAPTURE-DR state.
Reads the 32-bit device identification code. No programmable
supplementary identification code is provided.
32 bits. The format of the register is as shown in Figure B-3.
When the IDCODE instruction is current, the ID register is
selected as the serial path between TDI and TDO. There is no
parallel output from the ID register.
Part number
Figure B-3 ID code register format
12
11
Manufacturer identity 1
ARM DDI 0029G
1
0