SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 76

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
3.3.2
3-6
Sequential cycles
The ARM7TDMI processor can perform back-to-back, nonsequential memory cycles.
This happens, for example, when an
memory controller for the ARM7TDMI core, and your memory system is unable to
cope with this case, use the nWAIT signal to extend the bus cycle to allow sufficient
cycles for the memory system. See Stretching access times on page 3-29.
Sequential cycles are used to perform burst transfers on the bus. This information can
be used to optimize the design of a memory controller interfacing to a burst memory
device, such as a DRAM.
During a sequential cycle, the ARM7TDMI processor requests a memory location that
is part of a sequential burst. For the first cycle in the burst, the address can be the same
as the previous internal cycle. Otherwise the address is incremented from the previous
cycle:
•
•
Bursts of byte accesses are not possible.
A burst always starts with an N-cycle or a merged IS-cycle (see Nonsequential cycles
on page 3-5), and continues with S-cycles. A burst comprises transfers of the same type.
The A[31:0] signal increments during the burst. The other address class signals are
unaffected by a burst.
for a burst of word accesses, the address is incremented by 4 bytes
for a burst of halfword accesses, the address is incremented by 2 bytes.
nMREQ
D[31:0]
A[31:0]
Copyright © 1994-2001. All rights reserved.
MCLK
nRAS
nCAS
SEQ
instruction is executed. If you are designing a
Figure 3-2 Nonsequential memory cycle
N-cycle
a
ARM DDI 0029G
S-cycle
a+4