SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 151

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.6
ARM DDI 0029G
Multiply and multiply accumulate
The multiply instructions use special hardware that implements integer multiplication
with early termination. All cycles except the first are internal
The cycle timings are listed in the following tables:
•
•
•
•
In Table 6-5 to Table 6-8 on page 6-10:
•
multiply instruction cycle operations are listed in Table 6-5
multiply accumulate instruction cycle operations are listed in Table 6-6 on
page 6-9
multiply long instruction cycle operations are listed in Table 6-7 on page 6-10
multiply accumulate long instruction cycle operations are listed in Table 6-8 on
page 6-10.
m is the number of cycles required by the multiplication algorithm. See
Instruction speed summary on page 6-29.
Cycle
1
2
•
m
m+1
Cycle
1
2
•
m
Copyright © 1994-2001. All rights reserved.
Address
pc+2L
pc+3L
pc+3L
pc+3L
pc+3L
pc+3L
Address
pc+8
pc+8
pc+12
pc+12
Table 6-6 Multiply accumulate instruction cycle operations
nRW
0
0
0
0
0
nRW
0
0
0
0
MAS[1:0]
i
i
i
i
i
Table 6-5 Multiply instruction cycle operations
MAS[1:0]
2
2
2
2
Data
(pc+2L)
-
-
-
-
Data
(pc+8)
-
-
-
nMREQ
1
1
1
1
0
nMREQ
1
1
1
1
Instruction Cycle Timings
SEQ
0
0
0
0
1
SEQ
0
0
0
0
nOPC
0
1
1
1
1
nOPC
0
1
1
1
6-9