SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 73

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.2
ARM DDI 0029G
Bus interface signals
The signals in the ARM7TDMI processor bus interface can be grouped into four
categories:
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The clocking and clock control signals are:
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•
•
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The address class signals are:
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•
•
•
•
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The memory request signals are:
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The data timed signals are:
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The ARM7TDMI processor uses both the rising and falling edges of MCLK.
Bus cycles can be extended using the nWAIT signal. This signal is described in
Stretching access times on page 3-29. All other sections of this chapter describe a
simple system in which nWAIT is permanently HIGH.
clocking and clock control
address class signals
memory request signals
data timed signals.
MCLK
nWAIT
ECLK
nRESET.
A[31:0]
nRW
MAS[1:0]
nOPC
nTRANS
LOCK
TBIT.
nMREQ
SEQ.
D[31:0]
DIN[31:0]
DOUT[31:0]
ABORT
BL[3:0].
Copyright © 1994-2001. All rights reserved.
Memory Interface
3-3