SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 9

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

List of Tables
ARM7TDMI Technical Reference Manual
ARM DDI 0029G
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 4-1
Table 4-2
Change history .............................................................................................................. ii
Key to tables ........................................................................................................... 1-10
ARM instruction summary ....................................................................................... 1-12
Addressing modes .................................................................................................. 1-15
Operand 2 ............................................................................................................... 1-18
Fields ....................................................................................................................... 1-18
Condition fields ........................................................................................................ 1-19
Thumb instruction set summary .............................................................................. 1-21
Register mode identifiers .......................................................................................... 2-7
PSR mode bit values ............................................................................................... 2-15
Exception entry and exit .......................................................................................... 2-16
Exception vectors .................................................................................................... 2-21
Exception priority order ........................................................................................... 2-22
Bus cycle types ......................................................................................................... 3-5
Burst types ................................................................................................................ 3-7
Significant address bits ........................................................................................... 3-12
nOPC ...................................................................................................................... 3-12
nTRANS encoding .................................................................................................. 3-13
Tristate control of processor outputs ....................................................................... 3-21
Read accesses ........................................................................................................ 3-27
Use of nM[4:0] to indicate current processor mode ................................................ 3-32
Coprocessor availability ............................................................................................ 4-3
Handshaking signals ................................................................................................. 4-6
Copyright © 1994-2001. All rights reserved.
ix