SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 130

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface
5-8
•
Entry into debug state on watchpoint
Watchpoints occur on data accesses. A watchpoint is always taken, but the core might
not enter debug state immediately. In all cases, the current instruction completes. If the
current instruction is a multi-word load or store, with an LDM or STM, many cycles can
elapse before the watchpoint is taken.
When a watchpoint occurs, the current instruction completes, and all changes to the core
state are made, load data is written into the destination registers and base write-back
occurs.
Watchpoints are similar to Data Aborts. The difference is that when a Data Abort
occurs, although the instruction completes, the processor prevents all subsequent
changes to the ARM7TDMI processor state. This action allows the abort handler to cure
the cause of the abort and the instruction to be re-executed.
If a watchpoint occurs when an exception is pending, the core enters debug state in the
same mode as the exception.
Entry into debug state on debug request
The ARM7TDMI processor can be forced into debug state on debug request in either of
the following ways:
•
•
The DBGRQ pin is an asynchronous input and is therefore synchronized by logic inside
the ARM7TDMI processor before it takes effect. Following synchronization, the core
normally enters debug state at the end of the current instruction. However, if the current
instruction is a busy-waiting access to a coprocessor, the instruction terminates and
ARM7TDMI processor enters debug state immediately. This is similar to the action of
nIRQ and nFIQ.
An exception occurs, causing the processor to flush the instruction pipeline and
cancel the breakpoint. In normal circumstances, on exiting from an exception, the
ARM7TDMI core branches back to the next instruction to be executed before the
exception occurred. In this case, the pipeline is refilled and the breakpoint is
reflagged.
through EmbeddedICE Logic programming (see Programming breakpoints on
page B-45 and Programming watchpoints on page B-47)
by asserting the DBGRQ pin.
Note
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ARM DDI 0029G