ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 130

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

System reset
Table 62.
1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see
2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently
Table 63.
130/239
X: Pin is sampled
-: Pin is not sampled
Software Reset
Watchdog Reset
Synchronous Short Hardware Reset
Synchronous Long Hardware Reset
Asynchronous Hardware Reset
Asynchronous Power-On Reset
Watchdog Reset
Software Reset
flagged (see
Event
Reset event (continued)
The start-up configurations and some system features are selected on reset sequences as
described in
Table 63
reset modes.
BUSCON0 registers.
PORT0 latched configuration for the different reset events
Section 19.6
Sample event
(2)
(2)
x
x
0
1
x
x
0
1
describes what is the system configuration latched on PORT0 in the six different
for details).
0
0
1
1
0
0
1
1
Table 63
Figure 42
N Synch.
N Synch.
N Synch.
N Synch.
Y Synch.
Y Synch.
Y Synch.
Y Synch.
and
summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
Figure
X
X
X
-
-
-
Activated by internal logic for 1024 TCL
Activated by internal logic for 1024 TCL
42.
X
X
X
-
-
-
min
X
X
X
-
-
-
X
X
X
X
X
X
Not activated
Not activated
Not activated
Not activated
Not activated
Not activated
X
X
X
X
X
X
RSTIN
X
X
X
X
X
X
X
X
X
X
X
X
PORT0
X
X
X
X
X
X
max
Section 19.3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
for details).
0
0
X
X
X
X
0
0
0
0
0
0
-
-
WDTCON Flags
0
0
0
0
0
0
0
0
X
X
X
X
-
-
ST10F276Z5
X
X
X
X
0
0
0
0
0
0
0
0
-
-
X
X
X
X
1
1
1
1
1
1
1
1
-
-
X
X
X
X
0
0
0
0
1
1
1
1
-
-