ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 82

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Interrupt system
8.2
82/239
Table 42.
Exception and error traps list
Table 43
time.
Table 43.
1. The resets have the highest priority level and the same trap number.
2. Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority
3. All the class B traps have the same trap number (and vector) and the same lower priority compare to the
ASC1 Error
PLL Unlock / OWD
PWM1 Channel 3...0
Reset Functions
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps
Undefined Opcode
MAC Interruption
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Software Traps
TRAP Instruction
The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
level.
class A traps and to the resets.
Exception Condition
shows all of the possible exceptions or error conditions that can arise during run-
X-Interrupt detailed mapping (continued)
Trap priorities
(1)
:
(2)
(3)
:
:
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLBUS
STKOF
STKUF
ILLINA
Trap
Flag
NMI
XP0INT
STOTRAP
STUTRAP
NMITRAP
RESET
RESET
RESET
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
Vector
Trap
[002Ch - 003Ch]
0000h – 01FCh
XP1INT
in steps of 4h
Location
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
Vector
Any
XP2INT
[0Bh - 0Fh]
[00h - 7Fh]
x
Number
Trap
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Any
00h
00h
00h
02h
04h
06h
ST10F276Z5
XP3INT
Priority
Current
Priority
Trap*
x
CPU
x
x
III
III
III
II
II
II
I
I
I
I
I
I