ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 25

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ST10F276Z5
4
4.1
4.2
4.2.1
Internal Flash memory
Overview
The on-chip Flash is composed by two matrix modules each one containing one array
divided in two banks that can be read and modified independently one of the other: one
bank can be read while another bank is under modification.
Figure 4.
The write operations of the 4 banks are managed by an embedded Flash program/erase
controller (FPEC). The high voltages needed for program/erase operations are internally
generated.
The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first
512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining
320 Kbytes are accessed at 16-bit (see X-BUS).
Functional description
Structure
The following table shows the address space reserved to the Flash module.
Table 3.
IFLASH sectors
XFLASH sectors
Registers and Flash internal reserved
area
IFLASH (Module I)
Bank 1: 128 Kbyte
Bank 0: 384 Kbyte
8 Kbyte test-Flash
program memory
program memory
Description
Flash modules structure
Flash modules absolute mapping
+
I-BUS interface
Control section
Program/erase
HV and Ref.
generator
controller
0x09 0000 to 0x0D FFFF
0x0E 0000 to 0x0E FFFF
0x00 0000 to 0x08 FFFF
Addresses
X-BUS interface
XFLASH (Module X)
Bank 3: 128 Kbyte
Bank 2: 192 Kbyte
program memory
program memory
Internal Flash memory
512 Kbyte
320 Kbyte
64 Kbyte
Size
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