ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 30

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Internal Flash memory
4.4.2
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Table 7.
Flash control register 0 high
The Flash control register 0 high (FCR0H) together with the Flash control register 0 Low
(FCR0L) is used to enable and to monitor all the write operations for both the Flash
modules. The user has no access in write mode to the Test-Flash (B0TF). Besides, test-
Flash block is seen by the user in Bootstrap mode only.
FCR0H (0x0E 0002)
Table 8.
LOCK
BSY(1:0)
SMOD
SPR
WMS SUSP
RW
15
Bit
Bit
RW
14
WPG DWPG SER
RW
Flash control register 0 low (continued)
Flash control register 0 high
13
Flash registers access locked
When this bit is set, it means that the access to the Flash Control Registers FCR0H/-
FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read
access to the registers will output invalid data (software trap 009Bh) and any write
access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash: once it
is found low, the rest of FCR0L and all the other Flash registers are accessible by the
user as well.
Note that FER content can be read when LOCK is low, but its content is updated only
when also BSY bits are reset.
Bank 1:0 Busy (IFLASH)
These bits indicate that a write operation is running in the corresponding Bank of
IFLASH. They are automatically set when bit WMS is set. When these bits are set
every read access to the corresponding Bank will output invalid data (software trap
009Bh), while every write access to the Bank will be ignored. At the end of the write
operation or during a Program or Erase Suspend these bits are automatically reset
and the Bank returns to read mode. After a Program or Erase Resume these bits are
automatically set again.
Select module
If this bit is reset, the Write Operation is performed on XFLASH Module; if this bit is
set, the Write Operation is performed on IFLASH Module. SMOD bit is automatically
reset at the end of the Write operation.
Set protection
This bit must be set to select the Set Protection operation. The Set Protection
operation allows to program 0s in place of 1s in the Flash Non Volatile Protection
Registers. The Flash Address in which to program must be written in the FARH/L
registers, while the Flash Data to be programmed must be written in the FDR0H/L
before starting the execution by setting bit WMS. A sequence error is flagged by bit
SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB0-
0x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation.
RW
12
RW
11
10
Reserved
9
FCR
SPR
RW
8
SMOD
RW
Function
7
Function
6
5
4
Reserved
3
Reset value: 0000h
2
ST10F276Z5
1
0