ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 14

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Description
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Description
The ST10F276Z5 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip
CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions
per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides
on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock
generation via PLL.
The ST10F276Z5 is processed in 0.18 µm CMOS technology. The MCU core and the logic
is supplied with a 5 to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V
supply and I/Os work at 5 V.
The device is upward compatible with the ST10F269 device, with the following set of
differences:
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Flash control interface is now based on STMicroelectronics third generation of stand-
alone Flash memories (M29F400 series), with an embedded Program/Erase Controller.
This completely frees up the CPU during programming or erasing the Flash.
Only one supply pin (ex DC1 in ST10F269, renamed into V
is used for decoupling the internally generated 1.8 V core logic supply. Do not connect
this pin to 5.0 V external supply. Instead, this pin should be connected to a decoupling
capacitor (ceramic type, typical value 10 nF, maximum value 100 nF).
The AC and DC parameters are modified due to a difference in the maximum CPU
frequency.
A new V
EA pin assumes a new alternate functionality: it is also used to provide a dedicated
power supply (see V
the main Power Supply of the device (V
V
the range 4.5-5.5 V, and a dedicated embedded low power voltage regulator is in
charge to provide the 1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator
and the real-time clock module when not disabled. It is allowed to exceed the upper
limit up to 6 V for a very short period of time during the global life of the device, and
exceed the lower limit down to 4 V when RTC and 32 kHz on-chip oscillator are not
used.
A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here
SSC0, while the new one is referred as XSSC or simply SSC1). Note that some
restrictions and functional differences due to the XBUS peculiarities are present
between the classic SSC, and the new XSSC.
A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0,
while the new one is referred as XASC or simply as ASC1). Note that some restrictions
and functional differences due to the XBUS peculiarities are present between the
classic ASC, and the new XASC.
A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here
PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some
18
) is turned off for low power mode, allowing data retention. V
DD
pin replaces DC2 of ST10F269.
STBY
) to maintain biased a portion of the XRAM (16Kbytes) when
DD
and consequently the internally generated
18
) on the QFP144 package
STBY
voltage shall be in
ST10F276Z5