ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 188

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Electrical characteristics
23.7.1
188/239
6. DNL, INL, OFS and TUE are tested at V
7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not
8. Refer to scheme shown in
Conversion timing control
When a conversion starts, first the capacitances of the converter are loaded via the respec-
tive analog input pin to the current analog input voltage. The time to load the capacitances is
referred to as sample time. Next, the sampled voltage is converted in several successive
steps into a digital value, which corresponds to the 10-bit resolution of the ADC. During
these steps the internal capacitances are repeatedly charged and discharged via the V
pin.
The current that must be drawn from the sources for sampling and changing charges
depends on the duration of each step because the capacitors must reach their final voltage
level within the given time, at least with a certain approximation. However, the maximum cur-
rent that a source can deliver depends on its internal resistance.
The time that the two different actions take during conversion (sampling and converting) can
be programmed within a certain range in the device relative to the CPU clock. The absolute
time consumed by the different conversion steps is therefore independent from the general
speed of the controller. This allows adjusting the device A/D converter to the properties of
the system:
Fast conversion can be achieved by programming the respective times to their absolute
possible minimum. This is preferable for scanning high frequency signals. However, the
internal resistance of analog source and analog supply must be sufficiently low.
High internal resistance can be achieved by programming the respective times to a higher
value or to the possible maximum. This is preferable when using analog sources and supply
with a high internal resistance in order to keep the current as low as possible. However, the
conversion rate in this case may be considerably lower.
The conversion times are programmed via the upper 4 bits of register ADCON. Bit fields
ADCTC and ADSTC define the basic conversion time and in particular the partition between
the sample phase and comparison phases. The table below lists the possible combinations.
The timings refer to the unit TCL, where f
includes the conversion itself, the sample time and the time required to transfer the digital
value to the result register.
Table 96.
00
00
ADCTC
design characterization for all other voltages within the defined voltage range.
"LSB" has a value of V
For Port5 channels, the specified TUE (± 2LSB) is also guaranteed with an overload condition (see
specification) occurring on a maximum of 2 not selected analog input pins of Port5 and the absolute sum
of input overload currents on all Port5 analog input pins does not exceed 10 mA.
For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins:
When an overload condition occurs on a maximum of 2 not selected analog input pins of Port1 and the
input positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static
injection), the specified TUE is degraded (± 7LSB). To obtain the same accuracy, the negative injection
current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection.
selected channels with the overload current within the different specified ranges (for both positive and
negative injection current).
00
01
ADSTC
A/D Converter programming
TCL * 120
TCL * 140
AREF
Figure
/1024.
Sample
47.
AREF
TCL * 240
TCL * 280
= 5.0 V, V
Comparison
CPU
= 1/2TCL. A complete conversion time
AGND
= 0 V, V
TCL * 28
TCL * 16
DD
= 5.0 V. It is guaranteed by
Extra
TCL * 388
TCL * 436
Total conversion
ST10F276Z5
I
OV
AREF