ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 27

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ST10F276Z5
Table 5.
The table above refers to the configuration when bit ROMS1 of SYSCON register is set.
When Bootstrap mode is entered:
●
●
●
●
In Bootstrap mode, by default ROMS1 = 0, so the first 32KBytes of IFlash are mapped in
segment 0.
Example: In default configuration, to program address 0, user must put the value 01'0000h
in the FARL and FARH registers, but to verify the content of the address 0 a read to
00'0000h must be performed.
Table 6 shows the control register interface composition: this set of registers can be
addressed by the CPU.
Bank
B0
B1
B2
B3
Test-Flash is seen and available for code fetches (address 00’0000h)
User IFlash is only available for read and write accesses
Write accesses must be made with addresses starting in segment 1 from 01'0000h,
whatever ROMS1 bit in SYSCON value
Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
Flash modules sectorization (write operations or with roms1=’1’)
Bank 0 Test-Flash (B0TF)
Bank 0 Flash 0 (B0F0)
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
Bank 0 Flash 3 (B0F3)
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
Bank 0 Flash 8 (B0F8)
Bank 0 Flash 9 (B0F9)
Bank 1 Flash 0 (B1F0)
Bank 1 Flash 1 (B1F1)
Bank 2 Flash 0 (B2F0)
Bank 2 Flash 1 (B2F1)
Bank 2 Flash 2 (B2F2)
Bank 3 Flash 0 (B3F0)
Bank 3 Flash 1 (B3F1)
Description
0x000C 0000 - 0x000C FFFF
0x000D 0000 - 0x000D FFFF
0x000A 0000 - 0x000A FFFF
0x000B 0000 - 0x000B FFFF
0x0000 0000 - 0x0000 1FFF
0x0001 0000 - 0x0001 1FFF
0x0001 2000 - 0x0001 3FFF
0x0001 4000 - 0x0001 5FFF
0x0001 6000 - 0x0001 7FFF
0x0001 8000 - 0x0001 FFFF
0x0002 0000 - 0x0002 FFFF
0x0003 0000 - 0x0003 FFFF
0x0004 0000 - 0x0004 FFFF
0x0005 0000 - 0x0005 FFFF
0x0006 0000 - 0x0006 FFFF
0x0007 0000 - 0x0007 FFFF
0x0008 0000 - 0x0008 FFFF
0x0009 0000 - 0x0009 FFFF
Addresses
Internal Flash memory
32 KB
64 KB
64 KB
64 KB
64 KB
64 KB
64 KB
64 KB
64 KB
64 KB
64 KB
64 KB
64 KB
8 KB
8 KB
8 KB
8 KB
8 KB
Size
32-bit (I-BUS)
ST10 Bus
(X-BUS)
16-bit
size
27/239