ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 63

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ST10F276Z5
Table 33.
The error coming from the measurement of the 29 bit is:
It is maximal for the smallest BRP value and the smallest number of ticks in PT0. Therefore:
To improve precision, the aim is to have the smallest BRP so that the time quantum is the
smallest possible. Thus, an error on the calculation of time quanta in a bit time is minimal.
In order to do so, the value of PT0 is divided into ranges of 1450 ticks. In the algorithm, PT0
is divided by 1451 and the result is BRP.
The calculated BRP value is then used to divide PT0 in order to have the value of (1 +
Tseg1 + Tseg2). A table is made to set the values for Tseg1 and Tseg2 according to the
value of (1 + Tseg1 + Tseg2). These values of Tseg1 and Tseg2 are chosen in order to
reach a sample point between 70% and 80% of the bit time.
During the calculation of (1 + Tseg1 + Tseg2), an error e
This error is of 1 time quantum maximum.
To compensate for any possible error on bit rate, the (Re)Synchronization Jump Width is
fixed to 2 time quanta.
BRP
43
44
45
63
0
1
2
3
4
5
..
..
BRP and PT0 values
PT0_min
20416
20880
21344
1451
2901
4351
5801
7251
464
X
..
..
e
e
1 Max
1
= 6 / [PT0]
= 1.29%
PT0_max
63800
65250
66700
1450
2900
4350
5800
7250
8700
2
X
..
..
can be introduced by the division.
Possible timer overflow
Bootstrap loader
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