ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 203

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ST10F276Z5
23.8.12
Note:
23.8.13
PLL lock/unlock
During normal operation, if the PLL is unlocked for any reason, an interrupt request to the
CPU is generated and the reference clock (oscillator) is automatically disconnected from the
PLL input: In this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency F
crystal failure occurrence without risking to go into an undefined configuration: The system
is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between the reference clock and PLL input can be restored only by a hardware
reset, or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
The external RC circuit on RSTIN pin must be the right size in order to extend the duration of
the low pulse to grant the PLL to be locked before the level at RSTIN pin is recognized high:
Bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitely not sufficient
to get the PLL locked starting from free-running mode).
Conditions: V
Table 99.
1. Not 100% tested, guaranteed by design characterization.
Main oscillator specifications
Conditions: V
Table 100. Main oscillator specifications
1. Not 100% tested, guaranteed by design characterization
T
T
T
F
g
V
V
t
Symbol
STUP
Symbol
m
PSUP
LOCK
JIT
free
AV
OSC
Oscillator transconductance
Oscillation amplitude
Oscillation voltage level
Oscillator start-up time
PLL Start-up time
PLL Lock-in time
Single Period Jitter
(cycle to cycle = 2 TCL)
PLL free running
frequency
PLL lock/unlock timing
DD
DD
= 5 V ±10%, T
= 5 V ±10%, T
Parameter
Parameter
(1)
(1)
(1)
(1)
A
A
(1)
= –40 / +125
= –40 / +125 °C
Stable V
Stable V
starting from free-running mode
6 sigma time period variation
(peak to peak)
Multiplication factors: 3, 4
Multiplication factors: 5, 8, 10, 16
Peak to peak
Sine wave middle
Stable V
Stable V
DD
DD
Conditions
Conditions
DD
DD
and reference clock
and reference clock,
free
o
C
, resonator
- crystal
). This feature allows to recover from a
Min.
8
–
–
–
–
Electrical characteristics
V
DD
V
–500
Min.
250
500
DD
Value
–
–
Typ.
/ 2 –0.25
17
3
2
– 0.4
Value
Max.
+500
2000
4000
300
250
Max.
35
–
–
4
3
203/239
Unit
kHz
mA/V
µs
ps
Unit
ms
V