ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 133

MCU 16BIT 832KBIT FLASH 144-TQFP

ST10F276Z5T3

Manufacturer Part Number
ST10F276Z5T3
Description
MCU 16BIT 832KBIT FLASH 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F276Z5T3

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-TQFP, 144-VQFP
Cpu Family
ST10
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C
Total Internal Ram Size
68KB
# I/os (max)
111
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
24-chx10-bit
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Processor Series
ST10F27x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
68 KB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
497-6399 - KIT DEV STARTER ST10F276Z5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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ST10F276Z5
Note:
20.2.1
20.2.2
20.3
Before entering Power-down mode (by executing the instruction PWRDN), bit VREGOFF in
XMISC register must be set.
Leaving the main voltage regulator active during Power-down may lead to unexpected
behavior (ex: CPU wake-up) and power consumption higher than what specified.
Protected Power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected
Power-down mode is only activated if the NMI pin is pulled low when executing PWRDN
instruction (this means that the PWRD instruction belongs to the NMI software routine). This
mode is only deactivated with an external hardware reset on RSTIN pin.
Interruptible Power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set.
The Interruptible Power-down mode is only activated if all the enabled Fast External
Interrupt pins are in their inactive level.
This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt
request applied to one of the Fast External Interrupt pins, or with an interrupt generated by
the real-time clock, or with an interrupt generated by the activity on CAN’s and I
interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low
according the recommendations described in
An external RC circuit must be connected to RPD pin, as shown in the
Figure 43. External RC circuitry on RPD pin
To exit Power-down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40 ns.
Standby mode
In Standby mode, it is possible to turn off the main V
through the dedicated pin of the ST10F276Z5.
To enter Standby mode it is mandatory to held the device under reset: once the device is
under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital
interface is frozen in order to avoid any kind of data corruption.
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply (about 1.65 V in Standby mode) to bias all those circuits that shall remain
active: the portion of XRAM (16Kbytes for the ST10F276Z5), the RTC counters and 32 kHz
on-chip oscillator amplifier.
ST10F276Z5
RPD
Chapter 19: System
+
V
DD
R0
C0
220kΩ minimum
1µF Typical
DD
provided that V
Power reduction modes
reset.
STBY
Figure
is available
43.
2
C module
133/239

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