ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet - Page 224

• Manufacturer Part Number: ST10F276Z5T3
• Description: MCU 16BIT 832KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C
• Total Internal Ram Size: 68KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 24-chx10-bit
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Electrical characteristics
23.8.22
224/239
High-speed synchronous serial interface (SSC) timing modes
Master mode
V
Table 110. Master mode
1. Maximum baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to
2. Formula for SSC Clock Cycle time:
t
t
t
t
t
t
t
t
t
t
t
300
301
302
303
304
305
306
307p
308p
307
308
DD
Symbol
‘3h’, or with 48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum
baud rate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>.
Value ‘1h’ for <SSCBR> may be used only with CPU clock equal to (or lower than) 32 MHz (after checking
that timings are in line with the target slave).
t
Where <SSCBR> represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
300
= 5 V ±10%, V
= 4 TCL x (<SSCBR> + 1)
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SSC clock cycle time
SSC clock high time
SSC clock low time
SSC clock rise time
SSC clock fall time
Write data valid after shift
edge
Write data hold after shift
edge
Read data setup time
before latch edge, phase
error detection on
(SSCPEN = 1)
Read data hold time after
latch edge, phase error
detection on (SSCPEN = 1)
Read data setup time
before latch edge, phase
error detection off
(SSCPEN = 0)
Read data hold time after
latch edge, phase error
detection off (SSCPEN = 0)
3
SS
Parameter
= 0 V, T
300
is 125 ns (corresponding to 8Mbaud)
A
(2)
= -40 to +125 °C, C
(<SSCBR> = 0002h)
6.6MBd
Min.
37.5
150
– 2
Max. baud rate
63
50
25
–
0
40 MHz
(1)
@F
L
= 50 pF
Max.
CPU
150
10
15
–
–
=
2TCL + 12.5
t
300
(<SSCBR> = 0001h -
8TCL
4TCL
2TCL
Variable baud rate
Min.
/ 2 – 12
– 2
–
0
FFFFh)
262144 TCL
Max.
ST10F276Z5
10
15
–
–
Unit
ns