HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 11

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3
6.4
6.5
6.6
Section 7 User Break Controller (UBC)
7.1
7.2
7.3
7.4
7.5
Section 8 Bus State Controller (BSC)
8.1
6.2.5
Description of Registers.................................................................................................... 84
6.3.1
6.3.2
6.3.3
Interrupt Operation............................................................................................................ 89
6.4.1
6.4.2
Interrupt Response Time................................................................................................... 92
Data Transfer with Interrupt Request Signals ................................................................... 93
6.6.1
6.6.2
Overview........................................................................................................................... 95
7.1.1
7.1.2
7.1.3
Register Descriptions ........................................................................................................ 97
7.2.1
7.2.2
7.2.3
Operation .......................................................................................................................... 102
7.3.1
7.3.2
7.3.3
Use Examples.................................................................................................................... 105
7.4.1
7.4.2
7.4.3
Cautions on Use ................................................................................................................ 107
7.5.1
7.5.2
7.5.3
7.5.4
Overview........................................................................................................................... 109
8.1.1
8.1.2
8.1.3
Interrupt Exception Vectors and Priority Rankings ............................................. 79
Interrupt Priority Registers A–H (IPRA–IPRH) .................................................. 84
Interrupt Control Register (ICR).......................................................................... 86
IRQ Status Register (ISR).................................................................................... 87
Interrupt Sequence ............................................................................................... 89
Stack after Interrupt Exception Processing .......................................................... 91
Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 94
Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 94
Features................................................................................................................ 95
Block Diagram ..................................................................................................... 96
Register Configuration......................................................................................... 97
User Break Address Register (UBAR) ................................................................ 97
User Break Address Mask Register (UBAMR) ................................................... 98
User Break Bus Cycle Register (UBBR) ............................................................. 100
Flow of the User Break Operation ....................................................................... 102
Break on On-Chip Memory Instruction Fetch Cycle ........................................... 104
Program Counter (PC) Values Saved................................................................... 104
Break on CPU Instruction Fetch Cycle................................................................ 105
Break on CPU Data Access Cycle ....................................................................... 106
Break on DMA/DTC Cycle ................................................................................. 106
On-Chip Memory Instruction Fetch..................................................................... 107
Instruction Fetch at Branches............................................................................... 107
Contention between User Break and Exception Handling................................... 108
Break at Non-Delay Branch Instruction Jump Destination.................................. 108
Features................................................................................................................ 109
Block Diagram ..................................................................................................... 110
Pin Configuration................................................................................................. 111
........................................................................... 109
....................................................................... 95
Rev. 5.00 Jan 06, 2006 page ix of xx