HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 428

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
13.3.3
The multiprocessor communication function enables several processors to share a single serial
communication line for sending and receiving data. The processors communicate in the
asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.10 shows the example of communication among processors using the multiprocessor
format.
Rev. 5.00 Jan 06, 2006 page 406 of 818
REJ09B0273-0500
TDRF
Example: 8-bit data with parity and one stop bit
Serial
FER
data
Multiprocessor Communication
1
Start
bit
0
D0 D1
1 frame
Data
Figure 13.9 SCI Receive Operation
D7
Parity
RxI interrupt request
bit
0/1
Stop
bit
1
Start
bit
0
clears RDRF to 0.
data in RDR and
D0
handler reads
RxI interrupt
D1
Data
D7 0/1
Parity
bit
Framing error
ERI interrupt
Stop
generates
bit
request.
1
(marking
state)
Idle
1