HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 451

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
13.5.7
13.5.8
13.5.9
When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7
bit SCK output, but it cannot be copied to RDR.
When using an external clock source for the synchronization clock, update the TDR with the
DMAC, and then after five system clocks or more elapse, input a transmit clock. If a transmit
clock is input in the first four system clocks after the TDR is written, an error may occur
(figure 13.24).
Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as a start-up source.
Set TE = RE = 1 only when the external clock SCK is 1.
Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed
from 0 to 1.
When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the
RxD D7 bit SCK input, but it cannot be copied to RDR.
TDRE
SCK
Note: During external clock operation, an error may occur if t is 4 or less.
Constraints on DMAC Use
Cautions for Clock Synchronous External Clock Mode
Caution for Clock Synchronous Internal Clock Mode
Figure 13.24 Example of Clock Synchronous Transmission with DMAC
t
D0
D1
D2
Section 13 Serial Communication Interface (SCI)
D3
Rev. 5.00 Jan 06, 2006 page 429 of 818
D4
D5
D6
REJ09B0273-0500
D7

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