HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 436

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
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Quantity:
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Part Number:
HD64F7051SFJ20V
Manufacturer:
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Quantity:
20 000
Section 13 Serial Communication Interface (SCI)
13.3.4
In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver are independent, so full duplex communication is possible while
sharing the same clock. The transmitter and receiver are also double buffered, so continuous
transmitting or receiving is possible by reading or writing data while transmitting or receiving is in
progress.
Figure 13.16 shows the general format in clock synchronous serial communication.
Rev. 5.00 Jan 06, 2006 page 414 of 818
REJ09B0273-0500
RDRF
Example: Own ID matches data, 8-bit data with multiprocessor bit and one stop bit
Serial
MPIE
value
MPB
RDR
data
RxI interrupt request
interrupt), MPIE = 0
Clock Synchronous Operation
(multiprocessor
1
Figure 13.15 Example of SCI Receive Operation (ID Matches)
Start
bit
0
D0
(ID2)
Data
ID1
D1
and clears RDRF to 0
RxI interrupt handler
reads data in RDR
D7
MPB
1
Stop
bit
1
Start
bit
0
interrupt processing routine
D0
(data 2)
Station’s ID, so receiving
ID2
Data
continues, with data
received by the RxI
D1
D7
MPB
0
Stop
bit
1
(marking)
bit is again
set to 1
Data2
MPIE
Idling
1

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