HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 275

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Timer Interrupt Enable Register A (TIERA)
TIERA controls enabling/disabling of channel 0 input capture and overflow interrupt requests.
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4—Overflow Interrupt Enable (OVE0): Enables or disables OVI0 requests when the
overflow flag (OVF0) in TSR is set to 1.
Bit 3—Input Capture Interrupt Enable (ICE0D): Enables or disables ICI0D requests when the
input capture flag (ICF0D) in TSR is set to 1.
Bit 2—Input Capture Interrupt Enable (ICE0C): Enables or disables ICI0C requests when the
input capture flag (ICF0C) in TSR is set to 1.
Bit 4:
OVE0
0
1
Bit 3:
ICE0D
0
1
Bit 2:
ICE0C
0
1
Initial value:
Description
OVI0 interrupt requested by OVF0 is disabled
OVI0 interrupt requested by OVF0 is enabled
Description
ICI0D interrupt requested by ICF0D is disabled
ICI0D interrupt requested by ICF0D is enabled
Description
ICI0C interrupt requested by ICF0C is disabled
ICI0C interrupt requested by ICF0C is enabled
R/W:
Bit:
—
R
7
0
—
R
6
0
—
R
5
0
OVE0
R/W
4
0
Rev. 5.00 Jan 06, 2006 page 253 of 818
Section 10 Advanced Timer Unit (ATU)
ICE0D
R/W
3
0
ICE0C
R/W
2
0
REJ09B0273-0500
ICE0B
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
ICE0A
R/W
0
0