HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 168

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Direct Memory Access Controller (DMAC)
Bits 11–8—Resource Select 3–0 (RS3–RS0): These bits specify the transfer request source.
Bit 11:
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note: External request designations are valid only for channels 0 and 1. No transfer request
Bit 6—DREQ
to either low-level detection or falling-edge detection. This bit is valid only with CHCR0 and
CHCR1. For CHCR2 and CHCR3, this bit always reads as 0 and cannot be modified.
Even with channels 0 and 1, when specifying an on-chip peripheral module or autorequest as the
transfer request source, this bit setting is ignored. The sampling method is fixed at falling-edge
detection in cases other than auto-request.
Bit 6: DS
0
1
Rev. 5.00 Jan 06, 2006 page 146 of 818
REJ09B0273-0500
sources can be set for channels 2 or 3.
DREQ Select (DS): Sets the sampling method for the DREQ pin in external request mode
DREQ
DREQ
Bit 10:
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 9:
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
Low-level detection (initial value)
Falling-edge detection
Bit 8:
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
External request, dual address mode (initial value)
Prohibited
External request, single address mode. External address
space
External request, single address mode. External device
external address space.
Auto-request
Prohibited
ATU, compare-match 6 (CMI6)
ATU, input capture 0B (ICI0B)
SCI0 transmission
SCI0 reception
SCI1 transmission
SCI1 reception
SCI2 transmission
SCI2 reception
On-chip A/D0
On-chip A/D1
external device.