HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 719

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial Status Register (SSR)
Note:
Bit
7
6
5
Bit Name
Transmit data
register empty
(TDRE)
Receive data
register full
(RDRF)
Overrun error
(ORER)
Initial value:
* Only 0 can be written to clear the flag.
Bit name:
R/W:
Bit:
R/(W) *
TDRE
7
1
0
1
0
1
0
1
Value
R/(W) *
RDRF
Description
Valid transmit data has been written in TDR.
[Clearing conditions]
1. Read TDRE when TDRE = 1, then write 0 in TDRE
2. The DMAC writes data in TDR
There is no valid transmit data in TDR
[Setting conditions]
1. Power-on reset, or transition to hardware standby mode or software
2. TE is cleared to 0 in SCR
3. Data is transferred from TDR to TSR, enabling new data to be written
There is no valid receive data in RDR
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
2. Read RDRF when RDRF = 1, then write 0 in RDRF
3. The DMAC reads data from RDR
There is valid receive data in RDR
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
Receiving in progress, or completed normally
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
2. Read ORER when ORER = 1, then write 0 in ORER
Overrun error occurred during reception
[Setting condition]
Overrun error (reception of next serial data ends while RDRF = 1)
6
0
standby mode
in TDR
standby mode
standby mode
R/(W) *
ORER
5
0
Appendix A On-Chip Supporting Module Registers
H'FFFF81A4 (Channel 0)
H'FFFF81B4 (Channel 1)
H'FFFF81C4 (Channel 2)
R/(W) *
FER
4
0
Rev. 5.00 Jan 06, 2006 page 697 of 818
R/(W) *
PER
3
0
TEND
R
2
1
8/16
REJ09B0273-0500
MPB
R
1
0
(Initial value)
(Initial value)
(Initial value)
MPBT
R/W
0
0
SCI