HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 370

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 Advanced Pulse Controller (APC)
11.2
11.2.1
The pulse output port control register (POPCR) is a 16-bit readable/writable register.
POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode.
Bits 15 to 8—PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These
bits enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 15 to 8:
PULS7 to 0ROE
0
1
When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match
between the GR2B and TCNT2 values.
Bits 7 to 0—PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits
enable or disable 1 output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 7 to 0:
PULS7 to 0SOE
0
1
When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match
between the GR2A and TCNT2 values.
Rev. 5.00 Jan 06, 2006 page 348 of 818
REJ09B0273-0500
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Register Descriptions
Pulse Output Port Control Register (POPCR)
PULS7
ROE
15
0
PULS6
ROE
14
0
Description
0 output to APC pulse output pin (PULS7–PULS0) is disabled (Initial value)
0 output to APC pulse output pin (PULS7–PULS0) is enabled
Description
1 output to APC pulse output pin (PULS7–PULS0) is disabled (Initial value)
1 output to APC pulse output pin (PULS7–PULS0) is enabled
PULS5
ROE
13
0
PULS4
ROE
12
0
PULS3
ROE
11
0
PULS2
ROE
10
0
PULS1
ROE
9
0
PULS0
ROE
8
0
PULS7
SOE
7
0
PULS6
SOE
6
0
PULS5
SOE
5
0
PULS4
SOE
4
0
PULS3
SOE
3
0
PULS2
SOE
2
0
PULS1
SOE
1
0
PULS0
SOE
0
0