HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 212

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
HD64F7051SFJ20V
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Manufacturer:
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20 000
Section 9 Direct Memory Access Controller (DMAC)
9.4.2
In this example, an external request, serial address mode transfer with external memory as the
transfer source and an external device with DACK as the transfer destination is executed using
DMAC channel 1.
Table 9.8 indicates the transfer conditions and the setting values of each of the registers.
Table 9.8
Transfer Conditions
Transfer source: external RAM
Transfer destination: external device with DACK
Transfer count: 32 times
Transfer source address: decremented
Transfer destination address: (setting ineffective)
Transfer request source: external pin (DREQ1) edge
detection
Bus mode: burst
Transfer unit: word
No interrupt request generation at end of transfer
Channel priority ranking: 2
9.4.3
In this example, the on-chip A/D converter channel 0 is the transfer source and internal memory is
the transfer destination, and the address reload function is on.
Table 9.9 indicates the transfer conditions and the setting values of each of the registers.
Rev. 5.00 Jan 06, 2006 page 190 of 818
REJ09B0273-0500
Example of DMA Transfer between External RAM and External Device with
DACK
Example of DMA Transfer between A/D Converter and Internal Memory (Address
Reload On)
Transfer Conditions and Register Set Values for Transfer between External
RAM and External Device with DACK
0
1
3
Register
SAR1
DAR1
DMATCR1
CHCR1
DMAOR
Value
H'00400000
(access by DACK)
H'00000020
H'0201
H'00002269

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