HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 266

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
Bit 3—Input Capture/Compare-Match Flag (IMF3D): Status flag that indicates GR3D input
capture or compare-match.
Bit 3:
IMF3D
0
1
Bit 2—Input Capture/Compare-Match Flag (IMF3C): Status flag that indicates GR3C input
capture or compare-match.
Bit 2:
IMF3C
0
1
Bit 1—Input Capture/Compare-Match Flag (IMF3B): Status flag that indicates GR3B input
capture or compare-match.
Bit 1:
IMF3B
0
1
Rev. 5.00 Jan 06, 2006 page 244 of 818
REJ09B0273-0500
Description
[Clearing condition]
When IMF3D is read while set to 1, then 0 is written in IMF3D
[Setting conditions]
Description
[Clearing condition]
When IMF3C is read while set to 1, then 0 is written in IMF3C
[Setting conditions]
Description
[Clearing condition])
When IMF3B is read while set to 1, then 0 is written in IMF3B
[Setting conditions]
When the TCNT3 value is transferred to GR3D by an input capture signal while
GR3D is functioning as an input capture register
When TCNT3 = GR3D while GR3D is functioning as an output compare register
When the TCNT3 value is transferred to GR3C by an input capture signal while
GR3C is functioning as an input capture register
When TCNT3 = GR3C while GR3C is functioning as an output compare register
When the TCNT3 value is transferred to GR3B by an input capture signal while
GR3B is functioning as an input capture register
When TCNT3 = GR3B while GR3B is functioning as an output compare register
(Initial value)
(Initial value)
(Initial value)

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