HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 328

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
10.4
The ATU has 44 interrupt sources of five kinds: input capture interrupts, compare-match
interrupts, overflow interrupts, underflow interrupts, and interval interrupts.
10.4.1
IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the
IMF bit (ICF bit in case of channel 0) is set to 1 in the timer status register (TSR), and the TCNT
value is simultaneously transferred to the corresponding GR (ICR in the case of channel 0).
The timing in this case is shown in figure 10.30.
In the example in figure 10.30, a signal is input from an external pin, and input capture is
performed on detection of a rising edge.
Rev. 5.00 Jan 06, 2006 page 306 of 818
REJ09B0273-0500
Interrupt request signal
Interrupts
Status Flag Setting Timing
Internal input capture
Interrupt status flag
Input capture input
Figure 10.30 IMF (ICF) Setting Timing in Input Capture
IMF (ICF)
GR (ICR)
IMI (ICI)
TCNT
signal
CK
t
TICS
N
(input capture input setup time)
N

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