HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 47

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.3
Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV,
ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data.
Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code, but instead is stored in a
memory table. An immediate data transfer instruction (MOV) accesses the memory table using the
PC relative addressing mode with displacement.
2.3
2.3.1
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using
the pipeline system. Instructions are executed in 50 ns at 20 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data (table 2.2).
Table 2.2
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
SH7050 Series CPU
MOV.W
ADD
.DATA.W H'1234
Immediate Data Format
Instruction Features
RISC-Type Instruction Set
@(disp,PC),R1
R1,R0
.........
Sign Extension of Word Data
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Rev. 5.00 Jan 06, 2006 page 25 of 818
Example of Conventional CPU
ADD.W #H'1234,R0
REJ09B0273-0500
Section 2 CPU