HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 401

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in
the clock synchronous mode or when the MP bit is cleared to 0.
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Note: The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR)
Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source
and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and
CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin
function by using the pin function controller (PFC).
The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an
external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode
register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock
source, see table 13.10 in section 13.3, Operation.
Bit 3: MPIE
0
1
Bit 2: TEIE
0
1
after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit
to 0; or by clearing the TEIE bit to 0.
Description
Multiprocessor interrupts are disabled (normal receive operation) (initial
value). MPIE is cleared when the MPIE bit is cleared to 0, or the
multiprocessor bit (MPB) is set to 1 in receive data.
Multiprocessor interrupts are enabled. Receive-data-full interrupt
requests (RxI), receive-error interrupt requests (ERI), and setting of the
RDRF, FER, and ORER status flags in the serial status register (SSR)
are disabled until data with the multiprocessor bit set to 1 is received.
The SCI does not transfer receive data from the RSR to the RDR, does
not detect receive errors, and does not set the RDRF, FER, and ORER
flags in the serial status register (SSR). When it receives data that
includes MPB = 1, MPB is set to 1, and the SCI automatically clears
MPIE to 0, generates RxI and ERI interrupts (if the TIE and RIE bits in
the SCR are set to 1), and allows the FER and ORER bits to be set.
Description
Transmit-end interrupt (TEI) requests are disabled * (initial value)
Transmit-end interrupt (TEI) requests are enabled. *
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 379 of 818
REJ09B0273-0500